PCB Surface Finishes & Solder Mask Issues
PCB Surface finishes and solder mask issues that can arise due to those surfaces:
The RoHS environment today, immersion silver and ENIG replaces tin-lead. When tin-lead finishes were the norm, most solder mask clearances associated with the surface mount devices were “gang relieved,” which is to say there were no webs of solder mask material between the mounts. This tended to create situations where solder wicking occurred, shorting the mounts together.
Today, we have the capability to deal with solder mask webs between surface mounts as little as .004 to prevent wicking, wicking itself no longer occurs with the alternative surface finishes of today, such as ENIG, Immersion silver, and lead-free HASL.
There is some bad news; certain solder mask configurations are better suited to the alternative finishes of today. Today’s fabricators sometimes have to come up with creative process alternatives for solder mask configurations versus surface finishes such as ENIG and immersion silver.
An example would be: A customer would provide a solder mask clearance for a given feature on one side and no clearance on the other. If left as is, the solder mask feature that is tinted or covered on one side creates a cup that does not allow solutions through the barrel of the hole during the ENIG process, trapping the solutions and potentially resulting in blackened or oxidized holes.
At that fabrication level it can be handled a number of different ways, and the fabricator may contact you about a possible deviation such as:
Add a clearance of 1:1 or smaller than the drilled hole size. This would allow solution for the ENIG process to flow through the vias and avoid blackened or oxidized holes.
Perform a secondary via plugging process from the side with the 1:1 clearances. This would accomplish the customer’s original objective of having one side covered with mask and the other side exposed. In certain via-in-pad situations, the vias themselves are in the mount pad and clearances exist for the mount, but you want the via within plugged, fabricators can offer a process for plugging the vias (sometimes outsourced). It involves using an epoxy or a conductive fill in which the vias are first plated normally and then outsourced, where they are filled with either epoxy or conductive material and planarized to make flat.
If the customers desire is to plug a via adjacent to a surface mount but still clear the mount itself, this forces a situation in which the mask material bleeds through onto the mount from the opposing side, depositing mask material on the surface mount. Many times the fabricator will ask if these specific vias can be cleared of mask and not be plugged.
Defined Features:
A solder mask defined feature is created over an underlying copper land area where the mask clearance itself defines the feature. Avoid the use of solder mask define features whenever possible. Sometime the mask feature are not as well defined over metal, or worse, they will leave small deposits of mask that prevent the surface finish from adhering in these locations. In addition, without an underlying pad, the surface finish does not get full encapsulation of the pad, making it more difficult to assemble.
To prevent this a thermal tie under the mask clearance on the circuit layer so the edge of the mask clearance are over material, not copper, and you are still tied electrically to the metal by way of the thermal spokes. When this is not possible, for adhesion reason stick with green solder mask, because the green color holds up better that the other colors for “mask defined” features.
For more information on PCB Surface finishes and solder masks, please contact us at 412-828-5322 or click here to contact us online.
